Home > Products > Timing > Buffer > AU5411
AU5411Buffer
  • Frequency Range:
    up to 2.1GHz
  • Phase Noise:
    <50fs additive jitter
  • Input / Output:
    3:10 Differential buffer
  • Voltage:
    3.3/2.5Core, 1.8V~3.3V VDDIO
AU5411
Features

• Typical output skew between clock outputs is 30 ps.

• The input clock receiver in Au5410 can accept LVPECL, LVDS, LVCMOS, SSTL, HCSL and XTAL waveforms.

• Crystal frequencies from 8 MHz to 50 MHz are supported.

• Rystal input can be over driven with frequency up to 250 MHz in crystal bypass mode.

• Evel translation with core supply voltage of 3.3 V/2.5 V/1.8 V and 3.3 V/2.5 V/1.8 V/1.5 V output supply for LVCMOS output drivers.

System Benefits

• Low additive jitter/skew that lower system noise floor

• Programmable output clock type for design flexibility

• Wide operation voltage for design compatibility

• High integration reduces BOM cost, saves board space

• Low power consumption ideal for portable applications

Applications

• Wireless and Wired Infrastructure

• Networking and Data Communications

• Medical equipment

• Automation and test equipments

• High-End Audio/Video