• Quad PLL frequency translation from 1 of 4 inputs

• DPLL Programmable Bandwidth 1mHz- 4KHz

• Digitally Controlled Oscillator (DCO) Mode Frequency Step Resolution: 0.005 ppb

• Hitless input clock switching: Auto or manual, Maximum phase hit of only 50 ps

• ZDM supported with external feedback connection

• OTN/PTN

• BBU/RRU

• LAN Switch/Router with SyncE support

• Small Cell    

• Acceleration card    

• Lower phase noise minimizes bit error rate in the system

• Better signal integrity increases design margin and leads to faster time to market

• Higher clock tree integration reduces system BOM and increases overall reliability