• Quad PLL frequency translation from any of 4 inputs
• DPLL Programmable Bandwidth 0.09mHz- 4KHz
• Digitally Controlled Oscillator (DCO) Mode: Frequency step resolution 0.001 ppt, Phase adjustment accuracy < 1ps
• Hitless input clock switching: Auto or manual, Maximum phase hit of only 25 ps
• Internal ZDB Mode with <0.5 ns Input-to-Output delay variation
• JESD204B/C Support for data converter clocks
• OTN/PTN
• BBU/RRU
• 100/200/400G/800G Switch/Router with SyncE support
• Small Cell
• Acceleration card
• Lower phase noise minimizes bit error rate and increases design margin in 56G/112G PAM4 I/O systems
• Better signal integrity increases design margin and leads to faster time to market
• Higher clock tree integration reduces system BOM and increases overall reliability